000			00396nam a2200145Ia 4500
003			OSt
008			181001s2009 xx 000 0 und d
020			_a9788126519316
082			_a621.392 _bPAD
100			_aPadmanabhan, T. R.
245		0	_aDesign through Verilog HDL
260			_bJohn Wiley & Sons, _aNew Delhi: _c©2009
650			_aElectronics and Communication Engineering
942			_2ddc _cBK
999			_c5976 _d5976